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The Spartan UltraScale+ FPGA is designed to provide cost and energy-efficient compute. | Source: AMD
As robots and sensors proliferate, the need for robust compute has increased. Advanced Micro Devices Inc. yesterday announced its AMD Spartan UltraScale+ FPGA family. The company said the latest addition to its portfolio of field-programmable gate arrays, or FPGAs, and adaptive systems on chips, or SoCs, delivers cost and power-efficient performance for a wide range of I/O-intensive applications at the edge.
“For over 25 years, the Spartan FPGA family has helped power some of humanity’s finest achievements, from lifesaving automated defibrillators to the CERN particle accelerator advancing the boundaries of human knowledge,” stated Kirk Saban, corporate vice president of the Adaptive and Embedded Computing Group at AMD.
“Building on proven 16-nm technology, the Spartan UltraScale+ family’s enhanced security and features, common design tools, and long product lifecycles further strengthen our market-leading FPGA portfolio and underscore our commitment to delivering cost-optimized products for customers,” he added.
AMD claimed that its Spartan UltraScale+ devices offer a high I/O to logic cell ratio in FPGAs with built-in 28 nm and lower process technology. The Santa Clara, Calif.-based company said they consume as much as 30% less total power than its previous generation. The FPGAs also include the most robust set of security features in the cost-optimized portfolio, it asserted.
AMD optimizes Spartan UltraScale+ for the edge
The high I/O counts and flexible interfaces of the new Spartan UltraScale+ FPGAs enable them to efficiently interface with multiple devices or systems, said AMD. The company said this will help address “the explosion of sensors and connected devices” such as robots.
“Spartan UltraScale+ is primarily targeted for robot actuators, joint control, and camera sensors,” Rob Bauer, senior manager of cost-optimized silicon marketing at AMD, told The Robot Report. “IoT [Internet of Things] devices are growing 2.3X from 2022 to 2028, according to the FPGA Market Global Forecast. There’s a need for supply chain stability and longevity.”
“The high programmable I/O count enables interfacing with a very wide range of sensors, and that in combination with programmable logic allows sensor processing and control in a low-latency, deterministic, and real-time manner,” he explained. “Programmable I/O is made up of a combination of 3.3V HDIO, HPIO, and the new high-performance XP5IO capable of supporting 3.2G MIPI D-PHY.”
The FPGAs offer up to 572 I/Os and voltage support up to 3.3V. It enables any-to-any connectivity for edge connectivity for edge sensing and control applications.
AMD said its devices feature the “proven” 16nm fabric and support for a wide array of packaging, starting as small as 10x10mm. These provide high I/O density in an compact footprint.
In addition, the company said its portfolio provides the scalability to start with cost-optimized FPGAs and continue through to midrange and high-end products. It estimated that the Spartan UltraScale+ reduces power consumption by 30% in comparison with its 28 nm Artix 7 family by using 16 nm FinFET technology and hardened connectivity.
“Generational power improvement is up to 30%. This is already significant, as there could be multiple such devices used in a robot today that can be upgraded with lower-power, newer-generation devices,” Bauer said. “Additionally, as these devices are then expected to enable the nervous system of the robot by interfacing and putting out data between the sensors and the controller, which can now be done at a better overall power efficiency up to 60%.”
These devices are the first AMD UltraScale+ FPGAs with a hardened LPDDR5 memory controller and PCIe Gen4 x8 support, providing both power efficiency and future-ready capabilities for customers, said AMD.
Spartan UltraScale+ includes several security features
AMD said its new devices’ security features include:
- IP protection: Support for post-quantum cryptography (PQC) with NIST-approved algorithms offers state-of-the-art IP protection against evolving cyberattacks and threats. A physical unclonable function provides each device with a unique fingerprint for added security.
- Tampering prevention: PPK/SPK key support helps manage obsolete or compromised security keys, while differential power analysis helps protect against side-channel attacks. The devices contain a permanent tamper penalty to further protect against misuse.
- Uptime maximization: Enhanced single-event upset performance helps fast and secure configuration with increased reliability for customers, said AMD.
“We have many features in addition to PQC to enable secure authentication in post-quantum age,” Bauer said. “Spartan UltraScale+ devices are able to meet many of the requirements listed in IEC 62443, as it offers a long list of security features such as PUF, hardware root of trust, true random-number generator, AES-GCM-256, eFUSE, soft error mitigation, security monitor, DPA counter measures, temperature and voltage monitoring, tamper logging, JTAG monitoring, and more.”
Robotics and generative AI are contributing to chipset demand, according to Omdia, which estimated that the global market for dedicated SoCs could reach $866 million by 2028.
AMD said its entire portfolio of FPGAs and adaptive SoCs is supported by the AMD Vivado Design Suite and Vitis Unified Software Platform. This allows hardware and software designers to use “a single design cockpit from design to verification” to maximize the productivity benefits of these tools, it said.
The Spartan UltraScale+ FPGA sampling and evaluation kits will be available in the first half of 2025, according to AMD. Documentation is available now, and tools support started with AMD Vivado Design Suite in the fourth quarter of 2024.
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